As one of high-speed transmission systems for digital image signals, there is the standard of DVI (Digital Visual Interface) (hereinbelow, this standard shall be referred to as “DVI standard”, and the specification thereof shall be referred to as “DVI standard specification”). The DVI standard specification can be obtained from “http://www.ddwg.org/downloads.html”. A coding system which is handled in the present invention is stipulated on pages 28–29 in DVI standard specification Rev. 1.0 (hereinbelow, this coding system shall be termed “DVI coding system”). The circuits which form the foundation of the DVI coding system, are described in U.S. Pat. No. 6,026,124.
Shown in FIG. 1 is a flow chart of the DVI coding system.
The transmission system of DVI is a system wherein, on a transmission side, the 8-bit RGB (Red, Green, Blue) input signals of image data are respectively coded into 10-bit signals, the resulting parallel 10-bit data are respectively serialized, and four differential pair signals including a clock signal added to the serial data are transmitted.
The DVI coding system codes each 8-bit input signal into a 10-bit signal, thereby to minimize the probability of the transitions between adjacent two bits of the signal and also to balance a “H” level (hereinafter, also referred to as “1”) and a “L” level (hereinafter, also referred to as “0”). Minimizing the probability of the transitions between adjacent two bits decreases the number of times when the data change over in the case where the parallel 10-bit data is serialized and transmitted, which is effective to decrease the emission of superfluous electromagnetic waves. Balancing the “H” level and the “L” level eliminates the inter-pair DC-wise deviation of the signals transmitted as differential pairs.
Concretely, in a unit time, an 8-bit image data signal D[0:7] is input for one character, and 10-bit data q_out[0:9] is output for one T.M.D.S. character. “T.M.D.S. (Transition Minimized Differential Signaling)” is a coding system which forms the foundation of the DVI standard, and the “T.M.D.S. character” signifies the coded data of 10 bits.
The coding is done when a signal DE is at the “H” level.
Cnt(t) is a content which is held in an internal register at time “t” in order to keep the balance between a number of “1” and a number of “0” in a plurality of successive T.M.D.S. characters, and it is obtained as the sum of a value calculated by subtracting a number of “0” from a number of “1” and a content Cnt(t−1) held in the internal register at time (t−1). For example, when the signal is “1011000001” at the time “t”, a value, which is calculated in such a way that “−2” obtained by subtracting “6” as a number of “0” from “4” as a number of “1” is added to the content Cnt(t−1) held in the internal register at the time (t−1), becomes the value of the content Cnt(t).
By the way, in the figure, N1{x} indicates a formula which returns how many “1” are contained in a multi-bit variable “x”. Likewise, N0{x} returns how many “0” are contained in the multi-bit variable “x”. Further, q_m[] indicates a result produced by subjecting the 8-bit input signal D[0:7] to processing so as to decrease the number of the transitions between adjacent two bits thereof. The meaning of the number of the transitions between adjacent two bits will be explained, for example, in an 8-bit input signal “10010010”. When this input signal is viewed rightwards in succession, there are 5 parts where a value transits from “1” to “0” or from “0” to “1”, and hence, the number of the transitions between adjacent two bits is five. Besides, q13 out[0:9] indicates a 10-bit coded output signal further subjected to processing for keeping a DC balance.
As shown at S101 in FIG. 1, according to the standard specification, in order to minimize the probability of the transitions of the signal, the number of bits at the “H” level in the 8-bit input signal needs to be counted so as to discriminate “a case where the number of bits at the “H” level is larger than 4, or a case where the 0th bit is at the “L” level and where the number of bits at the “H” level is 4” from any other case. In the case where the number of bits at the “H” level is smaller, the number of the transitions between adjacent two bits can be decreased by coding with use of XORs, as shown at S102 in the figure. Besides, in the case where the number of bits at the “H” level is larger, the number of the transitions between adjacent two bits can be decreased by coding with use of XNORs, as shown at S103 in the figure. A circuit which incarnates step S101 in the figure in the standard specification, can be realized by combining a bit slice adder 2 and a condition discrimination circuit 3 as shown in a circuit diagram of FIG. 2. However, this circuit expends a long time because the circuit has a large number of stages of gates through which signals must pass till the final result is obtained. For example, in conventional logic circuits of CMOS scheme, in the case of each of full adders FA (7–10), signals need to pass two stages of gates for obtaining a carry signal C, and signals need to pass three stages of gates for obtaining a sum signal S, and in case of each of half adders HA (4–6), signals need to pass two stages of gates for obtaining a carry signal C, and signals need to pass two stages of gates for obtaining a sum signal S. Therefore, signals need to pass at most ten stages of gates till arrival at the condition discrimination circuit 3. In order to obtain the final result, signals need to pass several further stages of gates in the condition discrimination circuit 3.
Besides, as shown at step S102 or S103 in FIG. 1, according to the DVI standard, the number of the transitions is decreased by executing the processing of taking XOR or XNOR between 0th bit and 1st bit of the input bits and thenceforth taking XORs or XNORs between such computed results and the neighboring bits, respectively. When interpreted as stipulated in the DVI standard specification, a circuit for the above processing becomes as shown in FIG. 3. In the circuit, XNORs 11a–11g and XORs 12a–12g are connected in parallel, and either of their results is selected by a selector 13 at a succeeding stage. Also this circuit is disadvantageous in that the circuit has a large number of stages of gates through which signals pass till the determination of the last bit.
Next, according to the DVI standard, a judgment for balancing an output code DC-wise is formed at steps S106 and S107 as shown in FIG. 1. Concretely, there are formed a judgment on whether the content Cnt(t−1) of the internal register at the time (t−1) is plus, minus or zero, and a judgment on whether a number of bits at the “H” level is larger, a number of bits at the “L” level is larger, or a number of bits at the “H” level is equal to a number of bits at the “L” level, after the number of bits at the “H” level and the number of bits at the “L” level have been counted as to the 8-bit signal q_m[0:7] subjected to the processing of decreasing the number of the transitions between adjacent two bits. In accordance with the results of the judgments, the value of the data q_out[0:9] to be output to keep the DC balance is determined, and the internal register is updated at steps S110–S113 as shown in FIG. 1. A circuit for conducting operation which is close to that of a circuit incarnating such processing is illustrated in FIG. 7B of U.S. Pat. No. 6,026,124. A simplified block diagram for explaining the operation of a circuit based on the illustrated circuit, is shown in FIG. 4. First, the signal q_m[0:7] which has been coded so as to decrease the number of the transitions between adjacent two bits is divided into sets each consisting of 2 bits. As to the respective bit sets, whether bit values are “11” or “00” is evaluated by “11”·“00” detection circuits 14a–14d. If the value of each set of 2 bits is “01” or “10”, the DC balance is already kept within the 2 bits, and hence, the set is neglected. In accordance with the results of the evaluations, the numbers of “11” and “00” are respectively counted by counters 15 and 16. The differences between the counts of the two counters are computed by subtractors 17a, 17b, and the computed results, the content of the internal register and the value of data q_m[8] are evaluated by a condition decision circuit 18. Either one of output values of the subtractors 17a and 17b is selected by a selector 19 on the basis of the evaluated result, and the sum of the selected value, the output value of the condition decision circuit 18 and the value of a 4-bit register 21 is calculated by a 4-bit adder 20, so as to update the content of the 4-bit register 21 and to output a signal q_out[9] which indicates whether or not the final coded result is to be inverted.
This circuit operates upon receiving the outputs of the circuits for decreasing the number of the transitions, and therefore has the disadvantage that a long time is expended till the obtainment of the final result.
The present invention has an object to overcome the above disadvantages in the DVI coding system, and to provide a circuit which implements the system in a small hardware size, at high speed and with low power consumption.